Xilinx Vivado fails to elaborate


#1

Anybody know how to deal with Xilinx Vivado design tools erroring out during elaboration?

Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 59226cc8926b4937949e14df3864d18e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot p8e0_asmq_alu_tb_behav xil_defaultlib.p8e0_asmq_alu_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
Printing stacktrace…

[0] (KiUserExceptionDispatcher+0x2e) [0x7ffefef9dc5e]
[1] (ISIMC::Options::parseVlogcompCommandLine+0x6b84c) [0x7ff647c66cac]
[2] (ISIMC::VhdlCompiler::saveParserDump+0x37961) [0x7ff647b89581]
[3] (ISIMC::VhdlCompiler::saveParserDump+0x376a7) [0x7ff647b892c7]
[4] (ISIMC::VhdlCompiler::saveParserDump+0x37101) [0x7ff647b88d21]
[5] (ISIMC::VhdlCompiler::saveParserDump+0x2aba1) [0x7ff647b7c7c1]
[6] (ISIMC::VhdlCompiler::saveParserDump+0x2c9e2) [0x7ff647b7e602]
[7] (ISIMC::VhdlCompiler::saveParserDump+0x24782) [0x7ff647b763a2]
[8] (ISIMC::VhdlCompiler::saveParserDump+0x4fd7e) [0x7ff647ba199e]
[9] (ISIMC::VhdlCompiler::saveParserDump+0x4efad) [0x7ff647ba0bcd]
[10] (ISIMC::VhdlCompiler::saveParserDump+0x4c390) [0x7ff647b9dfb0]
[11] (ISIMC::VhdlCompiler::saveParserDump+0x4cdcd) [0x7ff647b9e9ed]
[12] (ISIMC::VhdlCompiler::saveParserDump+0x4d5b1) [0x7ff647b9f1d1]
[13] (ISIMC::Options::parseVlogcompCommandLine+0xdc29b) [0x7ff647cd76fb]
[14] (ISIMC::Options::parseVlogcompCommandLine+0xdbddd) [0x7ff647cd723d]
[15] (ISIMC::Options::parseVlogcompCommandLine+0xdb65d) [0x7ff647cd6abd]
[16] (ISIMC::VhdlCompiler::saveParserDump+0x8dabe) [0x7ff647bdf6de]
[17] [0x7ff647947bd5]
[18] [0x7ff647959d24]
[19] [0x7ff6479584b6]
[20] (ISIMC::Options::parseVlogcompCommandLine+0xac6f19) [0x7ff6486c2379]
[21] (BaseThreadInitThunk+0x14) [0x7ffefe6d3034]

Done
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 886.199 ; gain = 0.000
INFO: [USF-XSim-69] ‘elaborate’ step finished in ‘5’ seconds
INFO: [USF-XSim-99] Step results log file:‘C:/Users/tomtz/Documents/Xilinx/project_3/project_3.sim/sim_1/behav/xsim/elaborate.log’
ERROR: [USF-XSim-62] ‘elaborate’ step failed with error(s). Please check the Tcl console output or ‘C:/Users/tomtz/Documents/Xilinx/project_3/project_3.sim/sim_1/behav/xsim/elaborate.log’ file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 886.199 ; gain = 0.000
ERROR: [Common 17-39] ‘launch_simulation’ failed due to earlier errors.


#2

Please take a look at the elaborate.log file. That will have more clues as to what the real problem is. See this Xilinx forum post for a similar situation – https://forums.xilinx.com/t5/Simulation-and-Verification/USF-XSim-62-elaborate-step-failed-with-error-s-at-vivado-2015-2/td-p/645282

Bryan


#3

the log contained no information, but as we know that Xilinx doesn’t support VHDL 2008 I started to look for places where I am using VHDL that Xilinx can’t deal with and sure enough it was caused by the Xilinx tools not being compatible with the VHDL standard. So frustrating when you can’t rely on the tools and have to work around their short comings.